The present invention relates to a memory circuit and more particularly to a dual port memory circuit.
Random access memories (RAMs) utilizing the LSI technique have been used mainly as the main memories of computers and have come into widespread use in office automation devices, such as personal computers. Due to the remarkable reduction in the cost per bit of storage, MOS random access memories are used for processing video images, especially for displaying image on a CRT. A memory device used with such a display is connected between a CPU and the CRT. The CPU communicates with the RAM on a random access basis and supplies the display information to the RAM. The memory access time depends upon the speed of the CPU. Data transfer from the memory to the CRT is performed on a line-by-line sequential basis rather than on a random access basis. Moreover, the speed of such data transfer depends upon the display size of the CRT. Namely, the speed is determined in dependence upon the required resolution of the CRT. At present, the display size of a CRT frequently used in personal computers of 8-bit type is 640.times.400 dots (=256,000 dots) in one frame, and a cycle time of about 45 NS is required per dot.
The RAM for data display will hereinafter be referred to as a "VRAM". At present, such devices are inefficient for display applications. During the display period of the CRT, the data is sent to the CRT continuously at the data rate of 45 NS. During this period, the RAM cannot exchange data with the CPU so that the CPU can neither rewrite nor read the content of the VRAM. The data exchange between the VRAM and the CPU is limited to the blanking period during which no image is displayed on the CRT. As a result, the CPU and the system efficiency is remarkably low.
It has been proposed that RAMs having an input/output system for a CPU and an output system for a CRT are the best suitable for use as a VRAM. Such RAMs are called a "dual port memory".
A known dual port memory is structured such that a shift register is provided to the known RAM and a serial read operation to the CRT is performed via the shift register while performing the usual random access operation by the commonly provided input/output port of the RAM. However, according to such dual port memory, the order of serial read operations through the shift register is fixed. Namely, the serial read operation is always started from the first bit of the shift register, which first bit is located at the bit position closest to the output terminal and advanced towards the final bit of the shift register, which final bit is located at the bit position farthest from the output terminal.
In order to obviate the above problem, it has been proposed an improved dual port memory in which the serial read operation can be started from an arbitrary bit location. The details of this improved dual port memory is described in U.S. Pat. No. 4,633,441 issued to Ishimoto.
However, a counter or a shift register and a decoder for deciding a start bit position in accordance with column address information must be provided in the serial access port to achieve the above feature and therefore, an additional area for the counter and the decoder must be provided on a semiconductor chip on which the memory is formed, is necessitated to enlarge the whole size of the chip. This lowers the yields of the memories. Also, the above memory cause a large power consumption.